GF(2) Based Polynomials Multiplier Using An Efficient Systolic Multiplier
نویسندگان
چکیده
This paper presents an area-time-efficient systolic structure for multiplication over GF(2 m ) based on irreducible all-one polynomial (AOP). A novel cut-set retiming to reduce the duration of the critical-path to one XOR gate delay is used. Also the systolic structure can be decomposed into two or more parallel systolic branches, where the pair of parallel systolic branches has the same input operand, and they can share the same input operand registers. The field-programmable gate array synthesis results shows that the proposed design provides significantly less area-delay complexities over the best of the existing designs.
منابع مشابه
Efficient Bit - Parallel Systolic Multiplier over GF ( 2 m )
A bit parallel systolic multiplier in the finite field GF(2) over the polynomial basis where irreducible polynomial generate the field GF(2) is presented. The complexity of the proposed multiplier is compared in terms of area, latency and speed. The proposed multiplier has high throughput as compared with the traditional systolic multiplier. Moreover, this multiplier is highly regular, modular,...
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